The present invention relates generally to semiconductor memories and more particularly to a method of reading a memory cell of a semiconductor memory.
The access time of a semiconductor memory is typically determined by summing clock-to-word line delay and word line-to-output delay. However, where precharging or predischarging is required for an access operation, the access time is determined by summing the word line-to-output delay together with the greater of either the clock-to-word line delay or clock-to-precharge/predischarge termination time. In such instances, the access time is often largely dependent on the clock-to-precharge/predischarge termination time, as the clock-to-precharge/predischarge termination time is usually substantially greater than the clock-to-word line delay. Consequently, the access time of such semiconductor memories often cannot be improved by optimizing the clock-to-word line delay since the access time is determined using the clock-to-precharge/predischarge termination time, and not the clock-to-word line delay.
Further, as technology scales, bit line resistance becomes increasingly more dominant, lengthening the clock-to-precharge/predischarge termination time in, for example, ultra-deep sub-micron (UDSM) technologies at or below 90 nanometers (nm). This increases memory access time, particularly of memory instances that have a large number of memory cells coupled to each bit line.
Hence, there is a need for a precharging or predischarging scheme that is operable to reduce memory access times, and thereby increase semiconductor memory speeds.